Spring 2026
Digital Systems Laboratory
University of Illinois Urbana-Champaign
Designed and verified digital logic systems using SystemVerilog HDL workflows in Vivado with AMD Xilinx FPGAs.
- Finite State Machines
- Combinational & Sequential Logic
- SystemVerilog HDL
- Timing & Constraints
- Hardware Debugging
Course Focus
Building reliable digital components end-to-end: design, simulation, verification, and iteration against constraints.
What I built
FSM-driven modules and integrated logic blocks with an emphasis on testability.
Reflection
Strengthened my ability to think in discrete-time systems and validate designs through structured testbenches.